This project aims at enlarging the scope of automatic Instruction Set Extension (ISE). ISEs are special, complex instructions that are added to a processor in order to make it better targeted to a particular application to be served, resulting in higher performance and better power efficiency. Automatic ISE is the process of devising such extensions automatically from the application source code. The state of the art of automatic ISE indentification has advanced considerably in the past 15 years, including several papers by the applicant. On the other hand, several challenges still lay ahead, and the challenges here identified were inspired by reading a recent paper, that set out to understand the sources of inefficiencies of general-purpose processors, both in terms of performance and power. An important consideration is made at the end of the paper study: the only way to bridge the gap between sw execution, and dedicated hardware execution, is to specialize the baseline processor. The paper indeed adds more and more complex instruction to a baseline processor under consideration, identifying these instructions manually and terming them 'magic' because of their complexity, and achieving some outstanding performance improvements. This proposal aims at identifying those same instructions, but in an automatic way; i.e., devising algorithms that can identify and synthesize those instructions without programmer intervention. The charachteristics that make these instructions special, and beyond the current challenges of state of the art tools, are: they cluster 100s of original operations into a single instruction, they are tightly connected to custom data storage elements, they are built on top of vectorized code. These are indeed the challenges that this proposal wants to tackle. This proposal aims therefore at extending the state of the art in Instruction Set Extensions methodologies, combining them with compiler transformations such as vectorization, and finally analyzing the tradeoff of mapping such extensions on reconfigurable logic.