Computer Architectures and Logic Design
People
Course director
Description
The course visits the major techniques that have been devised in order to get high performance from a single processor, and, later on, from multi-processors. After the course you will understand the concepts of pipelined CPUs, cache architecture and optimization, Instruction-Level parallelism (Superscalar and VLIW architectures), Thread-Level parallelism (fine-grained, coarse-grained, simultaneous multithreading), Data-level parallelism (Vector architectures), and shared-memory multi-processing. Along the way, we will also review the main principles of gate-level logic design, in order for you to understand the basics of how hardware computes.
Objectives
Learn about the major architectural ideas that have made the incredible growth rate of modern microprocessors possible.
Teaching mode
In presence
Learning methods
Lectures, Assignments, Exams
Examination information
Final exam and assignments. Potentially a paper presentation and potentially a midterm exam.
Education
- Master of Science in Artificial Intelligence, Lecture, Elective, 1st year
- Master of Science in Artificial Intelligence, Lecture, Elective, 2nd year
- Master of Science in Computational Science, Lecture, 1st year
- Master of Science in Computational Science, Lecture, Elective, 2nd year
- Master of Science in Informatics, Lecture, Computer Systems, Elective, 1st year
- Master of Science in Informatics, Lecture, Computer Systems, Elective, 2nd year
- Master of Science in Informatics, Lecture, Information Systems, Elective, 2nd year
- Master of Science in Informatics, Lecture, Programming languages, Elective, 1st year
- Master of Science in Informatics, Lecture, Programming languages, Elective, 2nd year
- PhD programme of the Faculty of Informatics, Lecture, Elective, 1st year (4.0 ECTS)
