Architectural design and exploration of innovative coarse grained reconfigurable arrays

Reconfigurable Arrays combine the benefit of spatial execution, typical of hardware solutions, with that of programmability, present in microprocessors. As such, they could represent an efficient alternative to hardwired logic for implementing embedded applications, since they can provide hw acceleration without making the engineer commit to a non-modifiable design. Unfortunately, other drawbacks have kept reconfigurable logic from becoming a largely adopted solution in the high performance embedded field; among different factors, the performance and area gap that still exists with hardwired logic is certainly one of the most important. The problem of bridging this gap has been the focus of much research in the last decades, and a number of advancements have been made; in particular, Coarse Grain Reconfigurable Architectures (CGRAs) have been proposed in order to overcome the shortcomings of fine grain solutions such as FPGAs (Field Programmable Gate Arrays). CGRAs exhibit a larger cell granularity, therefore proving less flexible, but more efficient for arithmetic computations. This proposal aims at developing an innovative CGRA architecture that has the potential of providing an additional step in the direction of decreasing the above-mentioned gap further. There are two main reasons indicating that the proposed research has the potential of advancing the state of the art in CGRAs. The first point is that an innovative cell structure is envisioned, that is composed of a multiplicity of ALUs, flexibly connected, as opposed to a single ALU as is the case of most previous work. This feature enables the mapping of entire arithmetic/logic expressions, as opposed to single operations, onto one cell, and has the potential of providing enhanced area and delay results to the state of the art. The second important point is the presence of an exploration level in the proposed methodology. Having noticed that past works lack a systematic way of analysing and evaluating architectural choices, here, instead, architectural exploration of various parametric cell granularity and routing topologies is envisioned, enabled by retargetable compilation technology capable of mapping custom instructions onto different architectures. This makes it possible to study the effectiveness of different architectural choices in a systematic way. An initial study has been carried out by the proposer and by her PhD student - for whom this grant is requested - during the last 5 months, and has provided encouraging results.