An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512)
Contributo in atti di conferenza
An implementation of the hash functions SHA-256, 384 and 512 is presented, obtaining a high clock rate through a reduction of the critical path length, both in the Expander and in the Compressor of the hash scheme. The critical path is shown to be the smallest achievable. Synthesis results show that the new scheme can reach a clock rate well exceeding 1 GHz using a 0.13?m technology.
Atti di conferenza
GLSVLSI ''04: Proceedings of the 14th ACM Great Lakes symposium on VLSI