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An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512)

Additional information

Authors
Dadda L., Macchetti M., Owen J.
Type
Article in conference proceedings
Year
2004
Language
English
Abstract
An implementation of the hash functions SHA-256, 384 and 512 is presented, obtaining a high clock rate through a reduction of the critical path length, both in the Expander and in the Compressor of the hash scheme. The critical path is shown to be the smallest achievable. Synthesis results show that the new scheme can reach a clock rate well exceeding 1 GHz using a 0.13?m technology.
Conference proceedings
GLSVLSI ''04: Proceedings of the 14th ACM Great Lakes symposium on VLSI
Publisher
ACM Press, New York, USA
Start page number
421
End page number
425
Meeting place
Boston, MA, USA
ISBN
1-58113-853-9