A Configurable Monitoring Infrastructure for NoC-Based Architectures
Fiorin L., Palermo G., Silvano C.
In this brief, we propose a monitoring architecture for networks-on-chip that provides system information useful for designers to efficiently exploit, at design time and run-time, the system resources available in multiprocessor system-on-chip platforms. We focus on the analysis of the architectural details and design challenges of such a system, by describing powerful tools for monitoring information that can be used both at run-time for detecting dynamic changes in system behavior and at post-execution time for debugging and profiling of applications. This brief describes the design of the monitoring probes, together with the events detectable by them, and discusses an architecture for collecting, storing, and analyzing the information gathered during an application execution.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
hardware counters, networks-on-chip (NoCs), performance monitoring, systems-on-chip (SoCs).