PATUS: A Code Generation and Autotuning Framework for Parallel Iterative Stencil Computations on Modern Microarchitectures
Additional information
Authors
Christen M.,
Schenk O.,
Burkhart H.
Type
Article in conference proceedings
Year
2011
Language
English
Conference proceedings
2011 IEEE International Parallel Distributed Processing Symposium
Meeting name
IEEE International Parallel Distributed Processing Symposium
Meeting place
Sheraton Anchorage Hotel and Spa Anchorage, AK, USA
Meeting date
6 May - 20 May 2011
Keywords
computer architecture;computer graphic equipment;coprocessors;multiprocessing systems;parallel processing;partial differential equations;PATUS;PDE solvers;autotuning framework;code generation;complex hardware microarchitectures;graphics processing units;image processing;many core processors;meticulous architecture-specific tuning;multicore CPU;multicore processors;multigrid methods;parallel iterative stencil computations;stencil kernels;strategy-dependent parameters;Arrays;Hardware;Instruction sets;Kernel;Parallel processing;Three dimensional displays
