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A Design Flow and Evaluation Framework for DPA-resistant Instruction Set Extensions

Additional information

Authors
Regazzoni F., Cevrero A., Standaert F., Badel S., Kluter T., Brisk P., Leblebici Y., Ienne P.
Type
Book chapter
Year
2009
Language
English
Abstract
Power-based side channel attacks are a significant security risk, especially for embedded applications. To improve the security of such devices, protected logic styles have been proposed as an alternative to CMOS. However, they should only be used sparingly, since their area and power consumption are both significantly larger than for CMOS. We propose to augment a processor, realized in CMOS, with custom instruction set extensions, designed with security and performance as the primary objectives, that are realized in a protected logic. We have developed a design flow based on standard CAD tools that can automatically synthesize and place-and-route such hybrid designs. The flow is integrated into a simulation and evaluation environment to quantify the security achieved on a sound basis. Using MCML logic as a case study, we have explored different partitions of the PRESENT block cipher between protected and unprotected logic. This experiment illustrates the tradeoff between the type and amount of application-level functionality implemented in protected logic and the level of security achieved by the design. Our design approach and evaluation tools are generic and could be used to partition any algorithm using any protected logic style.
Book
Cryptographic Hardware and Embedded Systems (CHES)
Volume
5747
Month
September
Publisher
Springer Berlin Heidelberg
Series
Lecture Notes in Computer Science
Start page number
205
End page number
219
ISBN
978-3-642-04137-2
City
Lausanne, Switzerland