Towards a Reliability-aware Design Flow for Kahn Process Networks on NoC-based Multiprocessors
In order to satisfy performance and low power requirements of applications, embedded systems are becoming increasingly complex and highly integrated with various types of cores. As complexity increases and CMOS technology scales down into the deep-submicron domain, the rate of hard and soft faults in such systems increases. Such trend requires the reliability aspect to be incorporated as a design goal along with the more conventional goals such as performance, cost and power. In this paper, we investigate the reliability achieved by two system-level fault tolerance techniques, namely online task remapping and N-modular redundancy. By means of an analytical model of applications represented as Kahn Process Networks running on heterogeneous multiprocessors based on Networks-on-Chip, we evaluate these techniques with respect to the obtained level of reliability (mean-time-to-failure) and the overhead in computation (execution time) and communication (amount of data transfer on the network). By presenting a reliability estimation method, we enable a reliability-aware design flow on NoC-based MPSoCs.
10th Workshop on Dependability and Fault Tolerance (ARCS/VERFE''14)
Lecture Notes on Computer Science
fault tolerance, kahn process networks (KPN), networks-on-chip (NoC), reliability