A Monitoring System for NoCs
Fiorin L., Palermo G., Silvano C.
Article in conference proceedings
In this paper, we propose and discuss a monitoring architecture for Networks-on-Chip (NoCs) that provides system information useful for helping designers in efficiently exploiting resources available in new complex Multiprocessor System-on-Chip (MPSoC) platforms, and in understanding their behavior. We focus on the analysis of the architectural details and design challenges of such systems, by describing power- ful tools for detecting information that can be used both at run-time for detecting dynamic changes in system behavior and at post-execution time for debugging and profiling of applications. We detail the design of the probes monitoring the events and discuss an architecture for collection, storage, and analysis of information generated by them. We evaluate cost of the implementation of the system in terms of area and traffic overhead, and we present results obtained when monitoring a use-case multimedia application.
Proceedings of the Third International Workshop on Network on Chip Architectures (NoCArc''2010)
Atlanta, Georgia, USA
hardware counters, network-on-chip (NoC), performance monitoring, system-on-chip (SoC)