Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog
Additional information
Authors
Jain H.,
Kröning D.,
Sharygina N.,
Clarke E. M.
Type
Journal Article
Year
2008
Language
English
Journal
IEEE Trans. on CAD of Integrated Circuits and Systems
Volume
27
Number ( Month )
2
Pages (or article number)
366-379
