Gate-Stack Engineering in n-Type Ultrascaled Si Nanowire Field-Effect Transistors
Additional information
Authors
Luisier M.,
Schenk O.
Type
Journal Article
Year
2013
Language
English
Journal
IEEE Transactions on Electron Devices
Start page number
3325
End page number
3329
Keywords
field effect transistors;high-k dielectric thin films;leakage currents;nanowires;permittivity;silicon compounds;3D quantum transport solver;Si;SiO;conduction band offset;dielectric constant;effective mass approximation;gate leakage currents;gate stacks;gate-stack engineering;high-κ dielectrics;interfacial layer;size 0.5 nm to 0.6 nm;size 5 nm;ultrascaled nanowire field-effect transistors;Dielectrics;Effective mass;Field effect transistors;Leakage currents;Logic gates;Silicon;Device scaling;gate leakage;quantum transport simulation
