Gate-Stack Engineering in n-Type Ultrascaled Si Nanowire Field-Effect Transistors
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IEEE Transactions on Electron Devices
field effect transistors;high-k dielectric thin films;leakage currents;nanowires;permittivity;silicon compounds;3D quantum transport solver;Si;SiO;conduction band offset;dielectric constant;effective mass approximation;gate leakage currents;gate stacks;gate-stack engineering;high-κ dielectrics;interfacial layer;size 0.5 nm to 0.6 nm;size 5 nm;ultrascaled nanowire field-effect transistors;Dielectrics;Effective mass;Field effect transistors;Leakage currents;Logic gates;Silicon;Device scaling;gate leakage;quantum transport simulation