E4Bio - Energy-efficient heterogeneous systems for embedded bio-signal analysis

Wearable devices for bio-signal monitoring (Wireless Body Sensor Nodes, WBSNs) are fostering a revolution in healthcare provision, allowing for low-cost, continuous and unobtrusive monitoring of patients affected by chronic ailments. Most WBSNs are limited to sensing and wirelessly transmitting acquired data, hence delegating the interpretation of signals to labor-intensive manual inspection or, alternatively, to off-line automated applications executing on a server infrastructure. Recently, a new generation of smart WBSNs has emerged that, in addition to acquisition and communication, also embed Digital Signal Processing (DSP) capabilities on-node. This paradigm shift paves the road for truly autonomous health monitoring devices. The proposed project aims at unlocking the full potential of this scenario, by exploring novel energy-minimal DSP platforms devoted to embedded bio-signal analysis. Energy efficiency is, in fact, the main design objective for battery-operated WBSNs, because long-term operations must be granted within a highly constrained power envelope. This characteristic, in turns, demands a carefully tailored architecture for hosting the execution of on-node applications. The proposed research will follow a top-down approach, driven by the characteristic of bio-signal analysis algorithms to derive a domain-specific and ultra-low-power platform. Specifically, we will address the parallelism implicit in bio-signal DSP at two different levels. First, multiple processing cores will be employed to distribute the processing over different data sources, as well as during different computation phases. Second, we will explore how intensive segments of applications (computational kernels) can be efficiently implemented on a reconfigurable hardware accelerator. The flexibility of the accelerator will be at the arithmetic operation level, presenting a low area, critical path and energy overhead with respect to fixed-function implementation, as well as orders-of-magnitude faster configuration times compared to equivalent fine-grained solutions, such as FPGAs. Access to the reconfigurable mesh will be shared among the computing processors. In this context, we will explore how multiple requests of accelerated functions from different processors can be coalesced in a single configuration, transparently from the application perspective. The proposed system will seamlessly integrate these heterogeneous computing blocks by unifying the concepts of synchronization among processors and shared reconfiguration of the coarse-grained accelerator. To this end, we will develop a novel hardware/software synchronization and reconfiguration methodology, based on instruction set extensions supported by dedicated hardware elements. The project will result in a complete co-design and exploration environment comprising cycle-accurate simulators and RTL implementations of the heterogeneous systems, as well as a software infrastructure, able to compile real-world applications written in high-level C code onto the envisioned platform. We will also explore the scheduling algorithms allowing the automated mapping of computational kernels on the shared reconfigurable fabric. The framework will allow us to devise novel strategies for system-wide energy management based on frequency/voltage scaling and clock/power gating of the heterogeneous computing resources.