Gate-Stack Engineering in n-Type Ultrascaled Si Nanowire Field-Effect Transistors
Additional information
Authors
Luisier M.,
Schenk O.
Type
Journal Article
Year
2013
Language
English
Keywords
3D quantum transport solver, conduction band offset, Device scaling, dielectric constant, Dielectrics, Effective mass, effective mass approximation, Field effect transistors, gate leakage, gate leakage currents, gate stacks, gate-stack engineering, high-k dielectric thin films, high-κ dielectrics, interfacial layer, leakage currents, Logic gates, nanowires, permittivity, quantum transport simulation, Si, Silicon, silicon compounds, SiO, size 0.5 nm to 0.6 nm, size 5 nm, ultrascaled nanowire field-effect transistors
Journal
IEEE Transactions on Electron Devices
Pages (or article number)
3325-3329
