EGRA: A Coarse Grained Reconfigurable Architectural Template
Informazioni aggiuntive
Autori
Ansaloni G.,
Bonzini P.,
Pozzi L.
Tipo
Articolo pubblicato in rivista scientifica
Anno
2011
Lingua
Inglese
Sommario
Reconfigurable arrays combine the benefit of spatial execution, typical of hardware solutions, with that of programmability, present in microprocessors. When mapping software applications (or parts of them) onto hardware, however, fine-grain arrays, such as field-programmable gate arrays (FPGAs), often provide more flexibility than is needed, and do not implement coarser-level operations efficiently. Therefore, coarse grained reconfigurable arrays (CGRAs) have been proposed to this aim. Most CGRA design emerged in research present ad-hoc solutions in many aspects; in this paper we propose an architectural template to enable design space exploration of different possible CGRA designs. We called the template expression-grained reconfigurable array (EGRA), as its ability to generate complex computational cells, executing expressions as opposed to single operations, is a defining feature. Other notable EGRA characteristics include the ability to support heterogeneous cells and different storage requirements through various memory interfaces. The performed design explorations, as shown trough the experimental data provided, can effectively drive designers to further close the performance gap between reconfigurable and hardwired logic by providing guidelines on architectural design choices. Performance results on a number of embedded applications show that EGRA instances can be used as a reconfigurable fabric for customizable processors, outperforming more traditional CGRA designs.
Parole chiave
Application software, Boolean functions, CGRA design, coarse grained reconfigurable architectural template, Coarse grained reconfigurable architectures (CGRAs), design space exploration, field programmable gate arrays, field-programmable gate arrays, fine-grain arrays, FPGA, Hardware, logic design, memory interface, microprocessor chips, microprocessors, Programmable logic arrays, reconfigurable architectures, Reconfigurable logic, software mapping, Space exploration, template expression-grained reconfigurable array
Periodico
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Volume
19
Numero ( Mese )
6
Pagine (o numero dell’articolo)
1062-1074
ISSN
1063-8210
