Gate-Stack Engineering in n-Type Ultrascaled Si Nanowire Field-Effect Transistors
Informazioni aggiuntive
Autori
Luisier M.,
Schenk O.
Tipo
Articolo pubblicato in rivista scientifica
Anno
2013
Lingua
Inglese
Rivista
IEEE Transactions on Electron Devices
Pagina inizio
3325
Pagina fine
3329
Parole chiave
field effect transistors;high-k dielectric thin films;leakage currents;nanowires;permittivity;silicon compounds;3D quantum transport solver;Si;SiO;conduction band offset;dielectric constant;effective mass approximation;gate leakage currents;gate stacks;gate-stack engineering;high-κ dielectrics;interfacial layer;size 0.5 nm to 0.6 nm;size 5 nm;ultrascaled nanowire field-effect transistors;Dielectrics;Effective mass;Field effect transistors;Leakage currents;Logic gates;Silicon;Device scaling;gate leakage;quantum transport simulation
