Efficient AES implementations for ARM based platforms
Informazioni aggiuntive
Autori
Atasu K.,
Breveglieri L.,
Macchetti M.
Tipo
Contributo in atti di convegno
Anno
2004
Lingua
Inglese
Sommario
The Advanced Encryption Standard (AES) contest, started by the U.S. National Institute of Standards and Technology (NIST), saw the Rijndael [13] algorithm as its winner [11]. Although the AES is fully defined in terms of functionality, it requires best exploitation of architectural parameters in order to reach the optimum performance on specific architectures. Our work concentrates on ARM cores [1] widely used in the embedded industry. Most promising implementation choices for the common ARM Instruction Set Architecture (ISA) are identified, and a new implementation for the linear mixing layer is proposed. The performance improvement over current implementations is demonstrated by a case study on the Intel StrongARM SA-1110 Microprocessor [2]. Further improvements based on exploitation of memory hierarchies are also described, and the corresponding performance figures are presented.
Parole chiave
advanced encryption standard (AES), ARM microprocessor, cache memories, code optimisation
Titolo atti di convegno
SAC ''04: Proceedings of the 2004 ACM symposium on Applied computing
Editore
ACM Press, New York, USA
Luogo convegno
Nicosia, Cyprus
Pagine (o numero dell’articolo)
841-845
ISBN
1-58113-812-1
