Speeding Up AES By Extending a 32 bit Processor Instruction Set
Informazioni aggiuntive
Autori
Bertoni G. M.,
Breveglieri L.,
Farina R.,
Regazzoni F.
Tipo
Contributo in atti di convegno
Anno
2006
Lingua
Inglese
Sommario
Nowadays the need of speed in cipher and decipher operations is more important than in the past. This is due to the diffusion of real time applications, which fact involves the use of cryptography. Many co-processors for cryptography were studied and presented in the past, but only few works were addressed to the enhancement of the instruction set architecture (ISA) of the embedded processor. This paper presents an extension of the ISA of a 32 bit processor, that aims at speeding up the software implementations of the AES algorithm. After the identification of the most frequently executed and the most time consuming sections of the algorithm, a set of dedicated instructions is designed in order to improve the performances of the cipher operations. We validate our instruction set extension by measuring the speed up for different optimized implementations of AES using an ARM processor simulator, but the enhancements we propose are general enough to be applied to almost all 32 bit processors.
Parole chiave
cryptography, HW/SW co-design, instruction set extension
Titolo atti di convegno
ASAP ''06: Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP''06)
Editore
IEEE Computer Society
Luogo convegno
Washington, DC, USA
Pagine (o numero dell’articolo)
275-282
ISBN
0-7695-2682-9
