A Memory Unit for Priority Management in IPSec Accelerators
Informazioni aggiuntive
Autori
Dadda L.,
Ferrante A.,
Macchetti M.
Tipo
Contributo in atti di convegno
Anno
2007
Lingua
Inglese
Sommario
This paper introduces a hardware architecture for high speed network processors, focusing on support for Quality of Service in IPSec-dedicated systems. The effort is aimed at defining a secure system on chip environment, where the speed and security requirements are of utmost importance. In particular, a method is devised to introduce and support Quality of Service through priorities at this level. An architecture of a memory system that provides automatic priority management is proposed.
Parole chiave
accelerator, IPSec, priority, quality of service (QoS), security, system-on-chip (SoC), SystemC
Titolo atti di convegno
proceedings of ICC07. Glasgow, Scotland: IEEE Communications Society
Number ( Month )
June
Luogo convegno
Glasgow, Scotland
