Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration
Informazioni aggiuntive
Autori
Ansaloni G.,
Bonzini P.,
Pozzi L.
Tipo
Contributo in atti di convegno
Anno
2009
Lingua
Inglese
Sommario
Reconfigurable Architectures are good candidates for application accelerators that cannot be set in stone at production time. FPGAs however, often suffer from the area and performance penalty intrinsic in gate-level reconfigurability. To reduce this overhead, coarse-grained reconfigurable arrays (CGRAs) are reconfigurable at the ALU level, but a successful design needs more than computational power-the main bottleneck usually being memory transfers. Just like the integration of hardwired multiplier and memory blocks enabled FPGAs to efficiently implement digital signal processing applications, in this paper we study a customizable architecture template based on heterogeneous processing elements (multipliers, ALU clusters and memories) that provides enough flexibility to realize fast pipelined implementations of various loop kernels on a CGRA.
Parole chiave
Acceleration, Application software, Arithmetic, coarse-grained reconfigurable arrays, Computer architecture, digital signal processing, embedded processing acceleration, field programmable gate arrays, FPGA, gate-level reconfigurability, hardwired multiplier, heterogeneous coarse-grained processing elements, Informatics, Kernel, Logic arrays, memory blocks, reconfigurable architectures, Reconfigurable logic
Titolo atti di convegno
Design, Automation Test in Europe Conference Exhibition, 2009. DATE ''09.
Pagine (o numero dell’articolo)
542-547
