Gate-Stack Engineering in n-Type Ultrascaled Si Nanowire Field-Effect Transistors
Informazioni aggiuntive
Autori
Luisier M.,
Schenk O.
Tipo
Articolo pubblicato in rivista scientifica
Anno
2013
Lingua
Inglese
Parole chiave
3D quantum transport solver, conduction band offset, Device scaling, dielectric constant, Dielectrics, Effective mass, effective mass approximation, Field effect transistors, gate leakage, gate leakage currents, gate stacks, gate-stack engineering, high-k dielectric thin films, high-κ dielectrics, interfacial layer, leakage currents, Logic gates, nanowires, permittivity, quantum transport simulation, Si, Silicon, silicon compounds, SiO, size 0.5 nm to 0.6 nm, size 5 nm, ultrascaled nanowire field-effect transistors
Periodico
IEEE Transactions on Electron Devices
Pagine (o numero dell’articolo)
3325-3329
