Efficient AES implementations for ARM based platforms
Additional information
Authors
Atasu K.,
Breveglieri L.,
Macchetti M.
Type
Article in conference proceedings
Year
2004
Language
English
Abstract
The Advanced Encryption Standard (AES) contest, started by the U.S. National Institute of Standards and Technology (NIST), saw the Rijndael [13] algorithm as its winner [11]. Although the AES is fully defined in terms of functionality, it requires best exploitation of architectural parameters in order to reach the optimum performance on specific architectures. Our work concentrates on ARM cores [1] widely used in the embedded industry. Most promising implementation choices for the common ARM Instruction Set Architecture (ISA) are identified, and a new implementation for the linear mixing layer is proposed. The performance improvement over current implementations is demonstrated by a case study on the Intel StrongARM SA-1110 Microprocessor [2]. Further improvements based on exploitation of memory hierarchies are also described, and the corresponding performance figures are presented.
Conference proceedings
SAC ''04: Proceedings of the 2004 ACM symposium on Applied computing
Publisher
ACM Press, New York, USA
Start page number
841
End page number
845
Meeting place
Nicosia, Cyprus
ISBN
1-58113-812-1
Keywords
advanced encryption standard (AES), ARM microprocessor, cache memories, code optimisation
