Secure Memory Accesses on Networks-on-Chip
Additional information
Authors
Fiorin L.,
Palermo G.,
Lukovic S.,
Catalano V.,
Silvano C.
Type
Journal Article
Year
2008
Language
English
Abstract
Security is gaining relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses security aspects related to Network on Chip (NoC) architectures, foreseen as the communication infrastructure of next-generation embedded devices. In the context of NoC-based multiprocessor systems, we focus on the topic, not yet thoroughly faced, of data protection. In this paper, we present a secure NoC architecture composed of a set of Data Protection Units (DPUs) implemented within the Network Interfaces (NIs)1. The run-time configuration of the programmable part of the DPUs is managed by a central unit, the Network Security Manager (NSM). The DPU, similar to a firewall, can check and limit the access rights (none, read, write, or both) of processors accessing data and instructions in a shared memory. In particular, the DPU can distinguish between the operating roles (supervisor/user and secure/non secure) of the processing elements.We explore alternative implementations of the DPU and demonstrate how this unit does not affect the network latency if the memory request has the appropriate rights. We also focus on the dynamic updating of the DPUs to support their utilization in dynamic environments, and on the utilization of authentication techniques to increase the level of security.
Journal
IEEE Transactions on Computers
Volume
57
Number
9
Month
September
Start page number
1216
End page number
1229
Keywords
data protection, embedded systems, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), security
