Scheduling Small packets in IPSec Multi-accelerator Based Systems
Informazioni aggiuntive
Autori
Taddeo A.,
Ferrante A.
Tipo
Articolo pubblicato in rivista scientifica
Anno
2007
Lingua
Inglese
Abstract
IPSec is a suite of protocols that adds security to communications at the IP level. Protocols within the IPSec suite make extensive use of cryptographic algorithms. Since these algorithms are computationally very intensive, some hardware acceleration is needed to support high throughput. IPSec accelerator performance may heavily depend on the dimension of the packets to be processed. In fact, when packets are small, the time needed to transfer data and to set up the accelerators may exceed the one to process (e.g. to encrypt) the packets by software. In this paper we present a packet scheduling algorithm that tackles this problem. Packets belonging to the same Security Association are grouped before the transfer to the accelerators. Thus, the transfer and the initialization time have a lower influence on the total processing time of the packets. This algorithm also provides the capability of scheduling grouped packets over multiple cryptographic accelerators. High-level simulations of the scheduling algorithm have been performed and the results for a one-accelerator and for a two-accelerator system are also shown in this paper.
Rivista
Journal of Communication(JCM) Academy publisher
Volume
2
Numero
2
Mese
marzo
Pagina inizio
53
Pagina fine
60
Parole chiave
accelerator, HW/SW co-design, IPSec, scheduling algorithm, security
