UML in an Electronic System Level Design Methodology
Informazioni aggiuntive
Autori
Basu A. S.,
Lajolo M.,
Prevostini M.
Tipo
Contributo in atti di convegno
Anno
2004
Lingua
Inglese
Sommario
The interest in System-On-Chip (SoC) design using the Unifed Modeling Language (UML) has been growing significantly during the last couple of years. In this paper we would like to present a methodology that aims to address embedded systems design issues at multiple levels of abstraction and to support a function/architecture codesign process. Our approach integrates UML with high-level synthesis and hardware/software co-verification techniques in order to provide an automated flow for SoC design starting from system-level specifications down to hardware/software partitioning and integration. UML has been selected because it is platform independent and helps team members to share very efficiently relevant information during the various design phases, while high-level synthesis helps to evaluate constraints that the embedded system must satisfy: e.g. performance, power and cost starting from behavioral specifications. The paper aims to give a contribution towards SoC Design automation from System-level specification to hardware/software partitioning.
Parole chiave
HW/SW co-design, methodology, system-on-chip (SoC), unified modeling language (UML)
Titolo atti di convegno
UML-SOC''04
Number ( Month )
June
Luogo convegno
San Diego, California
Pagine (o numero dell’articolo)
47-52
