MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures
Silvano C., Fornaciari W., Palermo G., Zaccaria V., Castro F., Martinez M., Bocchio S., Zafalon R., Avasare P., Vanmeerbeeck G., Ykman-Couvreur C., Wouters M., Kavka C., Onesti L., Turco A., Bondi U., Mariani G., Posadas H., Villar E., Wu S. Y. C., Dongrui F., Hao Z., Shibin T.
Given the increasing complexity of Chip Multi-Processors (CMPs), a wide range of architecture parameters must be explored at design time to find the best trade-off in terms of multiple competing objectives (such as energy, delay, bandwidth, area, etc.) The design space of the target architectures is huge because it should consider all possible combinations of each hardware parameter (e.g., number of processors, processor issue width, L1 and L2 cache sizes, etc.). In this complex scenario, intuition and past experience of design architects is no more a sufficient condition to converge to an optimal design of the system. Indeed, Automatic Design Space Exploration (DSE) is needed to systematically support the analysis and quantitative comparison of a large amount of design alternatives in terms of multiple competing objectives (by means of Pareto analysis). The main goal of the MULTICUBE project consists of the definition of an automatic Design Space Exploration framework to support the design of next generation many-core architectures.
VLSI 2010 Annual Symposium
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